As semiconductor memory devices become more highly integrated with each advancement of the semiconductor memory device manufacturing process, it becomes highly likely that a failure occurs in circuitry of a semiconductor memory device. Since the semiconductor memory device with a failure cannot operate reliably, the semiconductor memory device needs to be discarded as a defective product, thereby reducing yield. Therefore, a semiconductor memory device includes extra redundancy cells so that a repair operation can replace a failed cell with a redundancy cell.
The repair operation of the semiconductor memory device will be described as follows.
First, a test is performed on cells in the semiconductor memory device to detect a fail address. The test may include a compression parallel test capable of determining whether any of a plurality of cells is defective. The compression parallel test is performed by sequentially selecting a plurality of word lines, storing data having the same logic level in a plurality of cells coupled to the word lines and then outputting at the same time the stored data, and comparing the logic levels of the data to detect a fail address.
Then, an address output circuit receives an input address including information of the fail address and outputs an output address in response to a pulse signal. A repair unit performs a repair operation on the word line selected by the output address.
Referring to FIG. 1, the relation between an input address and a pulse signal of a conventional semiconductor memory device will be described. In the following descriptions, it is assumed that a first input address INRA<1> is at a logic high level, a second input address INRA<2> is at a logic high level, a third input address INRA<3> is at a logic low level, and a fourth input address INRA<4> is at a logic high level.
First, a test signal TM is asserted to a logic high level to perform a compression parallel test. First to fourth pulse generation units sequentially generate first to fourth pulse signals PLS<1:4> from when a burst pulse signal BST is first generated. An address output circuit buffers the high-level first input address INRA<1> to output as a first output address OUTRA<1> in a period where the first pulse signal PLS<1> is at a logic high level, and buffers the high-level second input address INRA<2> to output as a second output address OUTRA<2> in a period where the second pulse signal PLS<2> is at a logic high level. Furthermore, the address output circuit buffers the low-level third input address INRA<3> to output as a third output address OUTRA<3> in a period where the third pulse signal PLS<3> is at a logic high level, and buffers the high-level fourth input address INRA<4> to output as a fourth output address OUTRA<4> in a period where the fourth pulse signal PLS<4> is at a logic high level.
The conventional semiconductor memory device generates the first to fourth pulse signals PLS<1:4> using four pulse generation units, receives the first to fourth input addresses INRA<1:4>, and outputs the first to fourth output addresses OUTRA<1:4> in response to the first to fourth pulse signals PLS<1:4>. As described above, in order to receive the first to fourth input addresses INRA<1:4> and output the first to fourth output addresses OUTRA<1:4>, four pulse signal generators are required. Furthermore, as the number of bits of the input address increases, the number of pulse signal generators also increases.